摘  要：硬件系統(tǒng)的規(guī)模越來越大，復(fù)雜程度越來越高, 對(duì)其進(jìn)行測(cè)試也越來越困難，邊界掃描技術(shù)很好地解決了傳統(tǒng)測(cè)試的不足。闡述了JTAG技術(shù)的基本原理，從設(shè)計(jì)方法、優(yōu)化策略及實(shí)現(xiàn)技術(shù)等方面，對(duì)基于JTAG的PCB可測(cè)性設(shè)計(jì)進(jìn)行了研究，給出了具體的實(shí)現(xiàn)方法，并實(shí)現(xiàn)了自動(dòng)測(cè)試系統(tǒng)中數(shù)據(jù)采集電路板的可測(cè)性設(shè)計(jì)。結(jié)果證明該方法有效縮短了測(cè)試時(shí)間,降低了維修測(cè)試費(fèi)用,具有較大的實(shí)用價(jià)值。   關(guān)鍵詞：電路板；邊界掃描；板級(jí)測(cè)試；可測(cè)性設(shè)計(jì)；JTAG   中圖分類號(hào)：TP311  文獻(xiàn)標(biāo)識(shí)碼：A  文章編號(hào)：1672-4984（2007）04-0077-04   Application of boundary scan technique in design of board-level test ZHOU Jie， ZHOU Shao-lei， PENG Xian， LEI Ming （Department of Control Engineering，Naval Aeronautical Engineering Academy，Yantai 264001，China）   Abstract: As the scale and complexity of hardware systems increase quickly, test becomes a difficult task. The BST technique can well make up the shortcoming of traditional test techniques. This article presented the basic principle of JTAG technique. The design for test of PCB based on JTAG was researched from designed method, optimization strategy, realization technique and so on. Some concrete implementing methods were given and the realization of the measurability design of the data collection circuit board of an automatic test system was also presented. The result shews that, by using this method, th time of test can be effectively shortened and the cost of maintenance and test can be reduced.   Key words: PCB； Boundary scan； Board level test； Design for test； JTAG